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Muniraj, N. J. R.
- Modeling and Performance Comparison of Nanobiosensor for Automated Disease Detection
Authors
1 Karpagam University, Coimbatore, IN
2 Electronics and Communication Engineering Department, Karpagam College of Engineering, Coimbatore, IN
Source
Biometrics and Bioinformatics, Vol 3, No 6 (2011), Pagination: 292-298Abstract
Automated disease detection and drug dosing is one of the most advanced emerging medical applications domain. With the advances in nanotechnology, nanobio sensors are being used to detect diseases. System level design and validation of automated disease detection unit is one of the challenging areas of study. In this paper, we develop a software based experimental setup for performance analysis of nanobio sensors for disease detection. Blood samples and fluids in human body are modeled using appropriate parameters and a mathematical model for nanobiosensor is developed. Performances of three nanobiosensors are analyzed and its properties are compared. Simulations of nanobiosensors are carried out using nanohub.org and Matlab. The results obtained are analyzed with simulation results in nanohub. The developed sensors are suitable for automated drug delivery unit.Keywords
Nanobio Sensors, Disease Detection, Nanowire, Mathematical Modeling.
- Efficient Approach for Delay Analysis in Digital Circuits
Authors
1 Department of ECE, Tejaa Shakthi Institute of Technology for Women, Coimbatore, Tamilnadu-641659, IN
Source
Biometrics and Bioinformatics, Vol 10, No 2 (2018), Pagination: 37-40Abstract
In this article, a fully digital system to analysis setup/hold time delays in digital circuits is presented. The digital circuit classified as two types: 1.combinational circuit, 2.sequentialcircuit.The proposed system benefits from easy to modify design, lowpower, smallarea, and simplecircuits. Delay element in digital system is timer. Her delay is propagation and contamination delay and etc. Delay analyzed in Xilinx ISE 10.1 software and ncsim in cadence tool,
It is implemented in very large scale integration (VLSI).here I am using ISCAS 85/89 benchmark circuits. Analysis and compare the delay in combinational circuit and sequential circuit. The system continuously monitor and analysis any setup/hold time delay in the combinational/sequential data path.
Keywords
Combinational and Sequential Circuits, Hold Time, Setup Time, Timing Analysis, Digital VLSI Circuit.References
- T. Okumura and M. Hashimoto, “Setup time, hold time and clock-to-Q delay computation under dynamic supply noise,” in Proc. IEEE CICC, Sep. 19–22, 2010, pp. 1–4.
- M. Hashimoto, J. Yamaguchi, and T. Sato et al., “Timing analysis considering temporal supply voltage fluctuation,” in Proc. Asia and South Pacific Design Automation Conf. (ASP-DAC 2005), Jan. 18–21, 2005, vol. 2, pp. 1098–1101 .
- Y.-S. Su, W.-K. Hon and C.-C. Yang et al., “Clock skew minimization in multi-voltage mode designs using adjustable delay buffers,” IEEE Trans. Comput.Aided Des. Integer. Circuits Syst., vol. 29, no. 12, pp. 1921–1930, Dec. 2010.
- C.-C. Kao and K.-C. Lin, “Clock skew minimization with adjustable delay buffers restriction,” in Proc. IEEE Int. Symp. Next-Generation Electron. (ISNE), Feb. 25–26, 2013, pp. 321–324.
- W.-P. Tu, S.-H. Huang and H.-H. Lu, “PVT-variations-tolerant clock design using self-correcting adjustable delay buffers,” in Proc. 2014 Int. Symp. Next-Generation Electron. (ISNE), May 7–10, 2014, pp. 1–2.
- K.-H. Lim, D. Joe, and T. Kim, “An optimal allocation algorithm of adjustable delay buffers and practical extensions for clock skew optimization in multiple power mode designs,” IEEE Trans. computer.-Aided Des. Integer. Circuits Syst., vol. 32, no. 3, pp. 392–405, Mar. 2013.
- K. Chae and S. Mu, “A dynamic timing error prevention technique in pipelines with time borrowing and clock stretching,” IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 61, no. 1, pp. 74–83, Jan. 2014.
- V. S.Melikyan, A.S.Sahakyan, and A. H.Shishmanyan etc.,” Data-clock setup and hold times margins correction method in high speed serial links,” in Proc. Computer. Sci. Inf. Technol. (CSIT), Sep. 23–27, 2013, pp. 1–5.
- M. Sasaki, N. N. M. Khan, and K. Asada, “A circuit for on-chip skew adjustment with jitter and setup time measurement,” in Proc. IEEE Asian Solid State Circuits Conf. (A-SSCC), Nov. 8–10, 2010, pp. 1–4.
- Crack Detection Using Image Processing Algorithm in MATLAB
Authors
1 Department of ECE, Tejaa Shakthi Institute of Technology for Women, Coimbatore, Tamilnadu-641659, IN
Source
Biometrics and Bioinformatics, Vol 10, No 3 (2018), Pagination: 56-57Abstract
Welding structures are nowadays used in many applications such as machineries in industry and in the form of bridges in civil structures. Crack in those structures results in loss of structural integrity which reduces a efficiency of a system in which the structure is used. Hence crack detection of a structure before implementation is important to reduce a defect. Here adaptive changing and morphology is used to detect a crack in structures.